This invention relates generally to a semiconductor memory and more particularly to memory array driving circuits capable of fast erasing of storage data in a memory.
Typical prior art techniques will be first explained with reference to a dynamic random access memory (DRAM) using CMOS (Complementary Metal Oxide Semiconductor) shown in FIG. 1 of the accompanying drawings, by way of example. In the drawing, the memory cells are of a folded bit line structure. The memory array has a matrix structure shown as consisting of four pairs of data lines and four word lines, to simplify the description. It has multiplexed address inputs, in order to receive external address signals in a time divided manner.
In FIG. 1, symbols MC.sub.00 to MC.sub.33 represent memory cells for storing data, D.sub.0 to D.sub.3 and DHD 0 to DHD 3 are data lines and W.sub.0 to W.sub.3 are word lines. An X decoder XDEC for selecting the word lines has a circuit construction such as shown in the drawing. PC.sub.0 to PC.sub.3 represent data line precharge circuits and SA.sub.0 to SA.sub.3 are sense amplifiers for amplifying the data read out from the memory cells. I/0 represents a common data line for data transfer to the memory cells and Y.sub.0 to Y.sub.3 are Y decoder output lines for switching the data lines and the common data lines.
A Y decoder YDEC for selecting and driving the Y decoder output lines has a circuit construction such as shown in FIG. 1. Symbol MA represents an amplifier for amplifying the data that is read out from the memory cell on the common data line. RASB and CASB are input buffer circuits for converting a row address strobe signal RAS and a column address strobe signal CAS from a TTL level to the power source level inside a chip, respectively, and consist of CMOS inverters or logical gates.
XAB and YAB are buffer circuits (i.e. X address buffer circuit and Y address buffer circuit) for row address signals (X address signals) and column address signals (Y address signals) from outside the chip, receive the address signals of the TTL level inputted thereto from outside the chip and convert them to signals of a chip internal voltage level, respectively. Each of these circuits consists of a CMOS inverter or a logic gate.
WEB is a buffer circuit for converting a write control signal WE (write enable signal) from the TTL level to the chip internal voltage level and consists of a CMOS inverter or a logic gate. DiB is a data input buffer circuit for converting an external write data from the TTL level to the chip internal voltage level and generates a true signal and a complementary signal. It consists of a CMOS inverter or a logic gate. DOB is a data output buffer circuit for outputting the data read out from the memory cell and consists of an inverter circuit. T.sub.1, T.sub.2, T.sub.3, T.sub.6 and T.sub.7 represent clock generators and each consists of a plurality of CMOS inverters or logic gates in accordance with a necessary delay time. Among them, T.sub.2 and T.sub.6 generate the true signal and the complementary signal, and T.sub.4 and T.sub.5 are internal address signal generators which generate true and complementary address signals and consist of a CMOS inverter or logic gate. In the drawing, MOS-FET with arrow represent PMOS with the others representing NMOS. V.sub. cc represents an internal voltage level and nodes with symbols are connected to the internal voltage line. V.sub.DP represents a 1/2V.sub.cc voltage and the nodes with this symbol are connected to a circuit generating this voltage.
The data read operation from the memory cell is made in the following manner. When the RAS signal changes from the High to Low level, the buffer circuit RASB generates the row (X) control signal .phi..sub.R.After the necessary delay time corresponding to this signal, a word line drive signal .phi..sub.X, sense amplifier drive signals .phi..sub.SA, .phi..sub.SA and a data line precharge signal .phi..sub.PC are generated. On the other hand, the external address signal Ai when the RAS signal changes from the High level to the Low level is taken into the chip by the X address buffer XAB and the X control signal (e.g. .phi..sub.R). This signal is turned to X system internal address signals a.sub.xi and a.sub.xi by the internal address signal generator T.sub.4. These signals are inputted to the X decoder XDEC to select one of the word lines W.sub.0 through W.sub.3. It will be assumed hereby that W.sub.0 is selected. After the word line is selected, the word line drive signal .phi..sub.x is generated and the selected word line W.sub.0 is driven from the Low level to the High level. At this time the data line precharge signal .phi..sub.PC changes from the High level to the Low level and the precharge circuit PC is turned OFF. Each data line is at 1/2 V.sub.cc (=V.sub.DP) which is the half of the power source voltage V.sub.cc.
When the word line W.sub.0 is driven, the memory cell signals are read out from all the memory cells MC.sub.00 .about.MC.sub.03 connected to the word line W.sub.0 to each data line connected thereto. In this case, the signals are read out to the data lines D.sub.0, D.sub.1, D.sub.2 and D.sub.3. Thereafter, the sense amplifier driving signal .phi..sub.SA changes from the Low level to the High level and .phi..sub.SA changes from the High level to the Low level to drive the sense amplifiers SA.sub.0 .about.SA.sub.3. These amplifiers amplify the memory cell signals read out to the data lines and set the level of the data line pair to 0 V and V.sub.cc in accordance with the memory cell signal. Next, when the CAS signal changes from the High level to the Low level, the buffer circuit CASB generates the column (Y) control signal .phi..sub.c and after the passage of a necessary delay time, a Y decoder output line drive signal .phi..sub.y is generated in response to this column control signal .phi..sub.c.
On the other hand, the external address signal Ai when CAS changes from the High level to the Low level is taken into the chip by the Y address buffer circuit YAB and the Y control signal (e.g. .phi..sub.c). This signal is turned to the Y internal address signals ay.sub.i, ay.sub.i the internal address signal generator T.sub.5. This signal is inputted to the Y decoder YDEC and selected one of the Y decoder output lines Y.sub.0 to Y.sub.3. It will be assumed hereby that Y.sub.0 is selected. Then, a Y decoder output line drive signal .phi..sub.y is generated and the selected Y decoder output line Y.sub.0 is driven from the Low level to the High level so that the data lines D.sub.0, D.sub.0 are connected to the common data line I/0 and the memory cell data are read out on the common data line I/0. Incidentally, though the common data line I/0 is precharged in advance to a certain voltage, a precharge circuit is not hereby illustrated. The data thus read out are amplified by an amplifier MA and outputted outside the chip through the data output buffer circuit DOB.
After the operations described above are complete, the RAS signal and CAS signal change from the Low level to the High level. Therefore, the X (row) control signal .phi..sub.R changes to the Low level, the word line driving signal .phi..sub.X changes to the Low level and the selected word line W.sub.0 changes to the low level, too. Accordingly, the data is stored once again in the memory cell. Thereafter the sense amplifier driving signal .phi..sub.SA changes to the Low level while .phi..sub.SA changes to the High level, thereby turning OFF the sense amplifier. Also, the Y (column) control signal .phi..sub.C changes to the Low level and the Y decoder output line driving signal .phi..sub.y changes to the High level in response to the former an the selected Y decoder output line Y.sub.0 changes to the Low level. Thereafter the data line precharge signal .phi..sub.PC changes to the High level, precharging the data line to the 1/2 V.sub.cc level. The common data line is precharged, too, and enters the waiting state.
The data write operation to the memory cell is made in the following way. In the write cycle, the procedures from the read-out of the memory cell signal and the amplification of the read signal by the sense amplifier are the same as those in the read cycle. Thereafter, when the WE signal changes from the High level to the Low level, the buffer circuit WEB generates the internal write control signal .phi..sub.W. This signal is turned to a true signal and a complementary signal by the timing pulse generator T.sub.6 so as to separate the common data line I/0 and the amplifier MA and to connect the common data line I/0 to the data input buffer DiB. The write data Di when the WE signal changes from the High level to the Low level is taken into the chip by the data input buffer circuit and the write control signal (e.g. .phi..sub.W) and turned to the true signal and the complementary signal. Accordingly, the write data is transferred to the common data line I/0. If the CAS signal changes from the High level to the Low level at this time, one of the Y decoder output, lines Y.sub.0 .about.Y.sub.3 is driven from the Low level to the High level. It will be assumed hereby that Y.sub.0 is driven. When Y.sub.0 changes to the High level, the write data is transferred to the data lines D.sub.0, D.sub.0 and written into the memory cell connected to the selected word line. Thereafter, when the RAS signal, CAS signal and WE signal change from the Low level to the High level, the word line level changes to the Low level in the same way as in the read cycle and the write data are stored in the memory cell. Thereafter the data line and common data line are precharged ane enter the waiting state.
As one of the prior art references related with the apparatus of this kind, mention can be made of IEEE J. Solid-State Circuits, vol. SC-19, No. 5 (1984), pp. 619-623.